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| FAST CMOS 18-BIT R/W BUFFER Integrated Device Technology, Inc. IDT54/74FCT162701T/AT FEATURES: * * * * * * * * * * * * * * 0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1A (max.) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack Extended commercial range of -40C to +85C Balanced Output Drivers: 24mA (commercial), 16mA (military) Reduced system switching noise Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25C Ideal for new generation x86 write-back cache solutions Suitable for modular x86 architectures Four deep write FIFO Latch in read path Synchronous FIFO reset DESCRIPTION: The FCT162701T/AT is an 18-bit Read/Write buffer with a four deep FIFO and a read-back latch. It can be used as a read/write buffer between a CPU and memory or to interface a high-speed bus and a slow peripheral. The Ato-B (write) path has a four deep FIFO for pipelined operations. The FIFO can be reset and a FIFO full condition is indicated by the full flag (FF). The B-to-A (read) path has a latch. A HIGH on LE, allows data to flow transparently from B-to-A. A LOW on LE allows the data to be latched on the falling edge of LE. The FCT162701T/AT has a balanced output drive with series termination. This provides low ground bounce, minimal undershoot and controlled output edge rates. FUNCTIONAL BLOCK DIAGRAM A1-18 18 OEBA RESET CLK WCE RCE FF FIFO (4 deep) LATCH LE OEAB 18 2915 drw 01 B1-18 The IDT logo is a registered trademark of Integrated Device Techology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES (c)1996 Integrated Device Technology, Inc. AUGUST 1996 DSC-2915/3 5.15 1 IDT54/74FCT162701T/AT FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS OEAB WCE A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 SO56-1 43 SO56-2 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RCE CLK B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 FF RESET OEAB WCE A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CERPACK TOP VIEW E56-1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RCE CLK B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 FF RESET SSOP/ TSSOP/TVSOP TOP VIEW 2915 drw 02 2915 drw 03 5.15 2 IDT54/74FCT162701T/AT FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION Pin Names A1-18 B1-18 CLK I/O I/O I/O I 18 bit I/O port. 18 bit I/O port. Clock for write path FIFO. Clocks data into FIFO when WCE is low, clocks data out of FIFO when RCE is low. When FIFO is full all further writes to the FIFO are inhibited. When FIFO is empty all reads from the FIFO are inhibited. CLK also resets the FIFO when RESET is low. Enable pin for FIFO input clock. Enable pin for FIFO output clock. Write path FIFO full flag. Goes low when FIFO is full. Synchronous FIFO reset - when low CLK resets the FIFO. The FIFO pointers are initialized to the "empty" condition and FIFO output is forced high (all ones). The FIFO full flag (FF) will be high immediately after reset. Output Enable pin for B port. Output Enable pin for A port. Read path latch enable pin. When high, data flows transparently from B port to A port, B data is latched on the falling edge of LE. 2915 tbl 01 Description WCE RCE FF RESET OEAB OEBA LE I I O I I I I ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max. VTERM(2) Terminal Voltage with Respect to -0.5 to +7.0 GND (3) Terminal Voltage with Respect to VTERM -0.5 to GND VCC +0.5 TSTG Storage Temperature -65 to +150 IOUT DC Output Current -60 to +120 Unit V V C mA CAPACITANCE (TA = +25C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0 pF 2915 lnk 03 NOTE: 1. This parameter is measured at characterization but not tested. 2915 lnk 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT. 5.15 3 IDT54/74FCT162701T/AT FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTIONAL DESCRIPTION: This device is useful as a read/write buffer for modular high end designs. It provides multi-level buffering in the write path and single deep buffering in the read path, and is suited to write back cache implementation. The read path provides a transparent latch. The four deep FIFO uses one clock with two clock enable pins, WCE and RCE to clock data in and out. The FIFO has an external full flag which goes LOW when the FIFO is full. Internal read and write pointers keep track of the words stored in the FIFO. A write attempt to a full FIFO is ignored. An attempt to read from an empty FIFO will have no effect and the last read data remains at the output of the FIFO. The FIFO may be reset by the synchronous RESET input. This resets the read and write pointers to the original "empty" condition and also sets all B outputs = 1. Simultaneous read and write attempts (clock data into FIFO as well as clock data out of FIFO) are possible except on FIFO empty and full boundaries. When the FIFO is empty, and a simultaneous read and write is attempted, the read is ignored while the write is executed. If the same is attempted when the FIFO is full, the write is ignored while the read is executed. Normal operation of the four deep FIFO in the write path is independent of the read path operation. Power, ground and data pin positions on the FCT162701T match those on the FCT16501T/162501T, allowing an easy upgrade. APPLICATIONS: 486 INTERFACE CacheRAM Coprocessor i486 FCT162701T A B DRAM W/R CLK CLK,WCE, RCE, RST PAL LE,OEBA, OEAB 2915 drw 04 Figure 1. FCT162701T Application Example 5.15 4 IDT54/74FCT162701T/AT FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 10%; Military: TA = -55C to +125C, VCC = 5.0V 10% Symbol VIH VIL II H II L IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) Input LOW Current (Input Input LOW Current (I/O (3-State Output pins) (5) VCC = Min., IIN = -18mA VCC = Max., VO = GND (3) -- Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC VI = GND VCC = Max. VO = 2.7V VO = 0.5V Min. 2.0 -- -- -- -- -- -- -- -- -80 -- -- Typ.(2) -- -- -- -- -- -- -- -- -0.7 -140 Max. -- Unit V V A 0.8 1 1 1 1 1 1 -1.2 -225 -- pins)(5) pins)(5) High Impedance Output Current Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current A V mA mV A 100 5 VCC = Max., VIN = GND or VCC 500 2915 lnk 04 OUTPUT DRIVE CHARACTERISTICS Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -16mA MIL. IOH = -24mA COM'L. IOL = 16mA MIL. IOL = 24mA COM'L. Min. 60 -60 2.4 -- Typ.(2) 115 -115 3.3 0.3 Max. 200 -200 -- 0.55 Unit mA mA V V 2915 lnk 05 NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is 5A at TA = -55C. 5.15 5 IDT54/74FCT162701T/AT FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPLY CHARACTERISTICS Symbol ICC ICCD (CLK) ICCD (O/P) IC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current due to clock switching (4) Dynamic Power Supply Current due to output switching(4) Total Power Supply Current (6) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. CLK Toggling Outputs Open 50% Duty Cycle One Bit Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle OEAB = GND; OEBA = VCC LE = WCE = RCE = GND RESET = VCC All Inputs Low VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle OEAB = GND; OEBA = VCC LE = WCE = RCE = GND RESET = VCC One Bit Toggling at fo = 5MHz 50% Duty Cycle Min. -- VIN = VCC VIN = GND -- -- VIN = VCC VIN = GND -- Typ.(2) 0.5 180 80 1.8 Max. 1.5 240 120 2.9 (5) mA Unit mA A/ MHz VIN = 3.4V VIN = GND -- 2.1 3.7 (5) VIN = VCC VIN = GND -- 2.2 3.5 VIN = 3.4V VIN = GND -- 2.7 5.0 NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN) = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (CLK) X fCP + ICCD (O/P) x fO NO ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at D ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fO = Output Frequency NO = Number of Outputs at fO 2915 tbl 06 5.15 6 IDT54/74FCT162701T/AT FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT162701T Parameter PROPAGATION DELAYS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 B1-18 to A 1-18 LE (Low to Hi) to A 1-18 CLK to FF CLK to B1-18 TIMES(3) Write path Write path Read path/latch Read path/latch Write path Write path Write path Write path Write path Write path Read path Read path Write path Read path/latch 2.5 0 3 0 3 0 3 0 1.5 1.5 1.5 1.5 3.0 3.0 -- -- -- -- -- -- -- -- 7.0 6.0 7.0 6.0 -- -- 2.5 0 3 0 3 0 3 0 1.5 1.5 1.5 1.5 3.0 3.0 -- -- -- -- -- -- -- -- 6.0 5.0 6.0 5.0 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2915 tbl 07 FCT162701AT Min.(2) 1.5 1.5 2 1 Max.(2) 5.5 4.7 6.0 5.2 Unit ns ns ns ns Test Conditions(1) Min.(2) 1.5 1.5 2 1 Max.(2) 6.5 5.7 7.0 6.0 Read path/latch Read path/latch Write path Write path SETUP & HOLD A1-18 to CLK (Low to Hi) Setup A1-18 to CLK (Low to Hi) Hold B1-18 to LE (Hi to Low) Setup B1-18 to LE (Hi to Low) Hold WCE, RCE (Low) to CLK Setup WCE, RCE (Low) to CLK Hold RESET (Low) to CLK Setup RESET (Low) to CLK Hold TIMES(3) ENABLE & DISABLE OEBA Low to A1-18 Enable OEBA High to A 1-18 Disable OEAB Low to B1-18 Enable OEAB High to B 1-18 Disable CLK HIGH or LOW Pulse Width LE HIGH Pulse Width MINIMUM PULSE WIDTHS NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Guaranteed but not tested. 5.15 7 IDT54/74FCT162701T/AT FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 7.0V SWITCH POSITION Test Open Drain Disable Low Enable Low All Other Tests Open 2915 lnk 07 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Switch Closed 2915 drw 04 SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU tH 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 2915 drw 05 LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE 1.5V tREM 1.5V 2915 drw 06 tSU tH PROPAGATION DELAY 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V 2915 drw 07 ENABLE AND DISABLE TIMES ENABLE DISABLE 3V 1.5V 0V 3.5V 0.3V tPHZ 0.3V 1.5V 0V VOH 0V 2915 drw 08 SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPLZ VOL NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns 5.15 8 IDT54/74FCT162701T/AT FAST CMOS 18-BIT R/W BUFFER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT FCT XXXX X Device Temperature Type Range X Package X Process Blank B PV PA PF E 162701T 162701AT 54 74 Commercial MIL-STD-883, Class B Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) CERPACK (E56-1) 18-Bit R/W Buffer -55C to +125C -40C to +85C 2915 drw 09 5.15 9 |
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